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VHDL-clock
- VHDL的程序设计模块,很有用那个,密码锁。-for vhdl!!
clock
- 多功能电子时钟,具有时间显示,时间调整等功能。-Multi-function electronic clocks, time display, time adjustment functions.
clock
- 可以实现时间调节,十二,二十四小时转换,定时,闹钟的时钟-Can be time-conditioning, 12, 24 hours conversion, time, alarm clock
clock
- 完成数字钟表的功能,可以实现整点报时,闹钟和设置时间-The completion of the functions of digital watches, you can bring the whole point timekeeping, alarm clock and set-up times
vhdl-digital-clock-design
- 设计一个具有特定功能的数字电子钟。准确计时,以数字形式显示h、min、s 的时间。小时的计时要求为二十四进位,分和秒的计时要求为六十进位。 该电子钟上电或按键复位后能自动显示系统提示00-00-00,进入时钟准备状态;第一次按电子钟功能键,电子钟从0时0分0秒开始运行,进入时钟运行状态;再次按电子钟功能键,则电子钟进入时钟调整状态,此时可利用各调整键调整时间,调整结束后可按功能键再次进入时钟运行状态。 -Designed with a specific function of a dig
clock_module_ref
- Xilinx clock module design
clock
- 电子课程设计数字钟的源代码,已在试验箱上实现,定义了管脚。可以调整时间-E-curriculum design digital clock source code has been achieved in the chamber, the definition of a pin. Can adjust the time
clock
- 电子时钟具有一般时钟所具有的所有功能,定时,报时,显示时间和日期以及秒表等等功能。-electric clock
vhdl
- 6位LED电子钟,非常实用实做过实验,自动报时,秒表-6 LED electronic clock, very useful experiment is done, automatic timer, stopwatch. . .
alarm-clock
- 基于vhdl的数字闹钟的设计。可实现计时、闹钟、调节时间功能。可以在FPGA上实现。-VHDL-based digital alarm clock design. Can achieve a time, alarm clock, adjust time function. FPGA implementation can be on.
VHDL
- DEMO2 数码管扫描显示电路/DEMO4 计数时钟 DEMO5 键盘扫描设计/DEMO6 波形发生器/DEMO7 用DAC实现电压信号检测/DEMO8 ADC电压测量/DEMO9 液晶驱动电路设计-DEMO2 digital tube display circuit scan/DEMO4 count clock scan design DEMO5 keyboard/DEMO6 Waveform Generator/DEMO7 implementation by DAC voltage si
clock
- 多功能计时器,具有校准,显示,可分别多秒,分小时,年,月,日操作和显示-a clock with multiple functions
shuzizhong
- 基于vhdl的数字钟完整工程文件,已在实验箱上实现-vhdl clock
clock
- 这是一个电子时钟的VHDL语言程序,非常好,注释也比较清晰,它包括电子时钟的所有功能。-This is an electronic clock VHDL language program, very good, the Notes are also clear, which includes all the features of the electronic clock.
clock
- 本文档采用VHDL语言编写了一个数字时钟的程序,该数字时钟采用24小时制计时,可以实现整点报时,时间设置,闹钟等功能。最小分辨率为1秒。-VHDL language in this document using a digital clock to prepare the procedure, the digital clock 24-hour time system, you can bring the whole point of time, time settings, alarm clo
shift
- E1接收部分主要功能是实现从输入的差分线路数据中恢复出2.048M线路时钟并将数据解码输出。包括解码和线路时钟恢复两模块。-E1 to receive some of the major functions of the difference from the input data lines to recover a clock and data lines 2.048M decoder output. Including decoding and clock recovery circuit
clock
- 一个简单那的数字电子钟 VHDL的,很简单,适合刚入门的新手练习-It' s a simple VHDL digital electronic clock, simply put, the new entry just for practice
clock
- 由锁相环(PLL)产生所需的2分频与4分频时钟8分频时钟 clk.qpf为可执行主程序 -By the phase-locked loop (PLL) have the necessary 2-and 4-frequency clock frequency of 8 minutes for Executable clk.qpf main clock
clock
- 电子时钟简单设计模板,内含源代码,并可实现简单计时-Electronic Clock simple design template, containing the source code, and with a simple timing
clock
- 采用Verilog HDL语言编写的多功能数字钟,包括四个功能:时间显示与设置、秒表、闹钟、日期显示与设置.-Using Verilog HDL language multi-functional digital clock, including the four functions: time display and settings, stopwatch, alarm clock, date display and settings.